Implementation of hard IP modules in integrated circuits provides various benefits. For example, in contrast to a PLD implementation, by implementing hard IP, a significant savings in terms of logic elements is achieved. This can translate to savings in silicon area and potentially to reduced power consumption. A further advantage is that by implementing tested and proven hard IP, a designer is assured of a robust functional block that may lead to shorter design times.
In implementing certain hard IP, traditional approaches have placed certain fixed design constraints. For example, so as to assure the integrity of the hard IP, certain design changes have been prohibited. When implementing certain hard IP that may interface with communications channels, traditional approaches may have required dedicated assignments of communications channels. For example, when implementing PCIe functionality through hard IP, a traditional approach has been to dedicate a fixed number of communication channels to each PCIe block. This approach may be disadvantageous because it can result in the under-utilization of communication channels where certain of the PCIe blocks, for example, do not use all of their dedicated channels. More particularly, where one block does not use all of its channels, these unused channels cannot be used by other blocks to provide improved functionality.
There exists a need in the art for the flexible assignment of communication channels among hard IP blocks. There is a further need to avoid the under utilization of available communication channels.